The present invention relates to semiconductor device manufacturing technology, and, more particularly, to a technique which is useful for providing an improvement in the throughput of the dicing process after the block molding process in the manufacture of a semiconductor device.
A conventional dicing scheme is based on the formation of reference division marks on a substrate, with multiple electronic parts being integrated thereon, at the same time and in the same manner as the formation of a wiring line pattern, after which dicing of the substrate into individual electronic devices is carried out in accordance with the reference marks, as shown in Japanese Patent Application Laid-Open No. Hei 11(1999)-274357 (FIG. 4).
Conventional electronic devices formed of multiple electronic parts on a mother substrate without the formation of resin have marks to be used for dicing, as shown in Japanese Patent Application Laid-Open No. 2002-246336 (FIG. 2).